1. Field of the Invention
This invention pertains to integrated circuits using MOS or CMOS circuitry and in particular to a flip-flop circuit having a built-in enable function in a minimum size implementation and no increase in power dissipation.
2. Description of the Prior Art
In many application a shift register, or a counter, or a flip-flop, needs to be maintained in its present state for a certain number of clock cycles determined by the length of an enable signal, E. In the prior art, this has required the addition of extra gating or a stopping of the local clock. Extra gating takes up more area on the surface of an integrated circuit and in many cases dissipates additional power. Stopping the local clock is generally not a good practice because it introduces clock skew between the local clock and the system clock.
An example of gating can be found in U.S. Pat. No. 3,993,919.
An example of a single flip-flop integrated with circuitry which enables the single flip-flop to be triggered by each of several individual clocked functions without interfering with one another is disclosed in U.S. Pat. No. 4,224,533. The flip-flop of this patent has a double stack of transistors in its trigger circuit and an asynchronous clock.